The present invention is directed to manufacturing of semiconductor devices, and especially to dynamically controlling an etch process to improve product quality and yield as well as to improve efficiency of the process overall.
A typical etch process for a semiconductor device includes several etch process segments, or steps: (1) a hard mask etch (HM), (2) a hard mask over etch (HMO), an ASH resist away step, a polysilicon breakthrough (PBT), a polysilicon main etch step (PME), a polysilicon end point step (PEP) and a polysilicon over etch step (POE). The hardmask over etch step (HMO) is typically used to control the critical dimension (CD) of the gate of a semiconductor device, such as a transistor. The hardmask over etch (HMO) processing time, that is the time during which the semiconductor device is subjected to the HMO etch bath, may vary from lot to lot among various batches of processed material. Because the HMO step time varies from lot to lot due to the variations in the printed lithographic CD and because the HMO step consumes polysilicon material, the thickness of polysilicon material present for subsequent etch process segments also varies from lot to lot. As a consequence there is a risk that at some locations on the wafer the oxide under the polysilicon material will be exposed for a long period of time during the PEP step or even in some cases during the PME etch step. In such situations punchthrough or microtrenching through the oxide into the underlying silicon substrate can occur near the transistor gate. That is, because of the variance from lot to lot in processing time the HMO process usually consumes polysilicon material, and the thickness of polysilicon material present for subsequent etch process segments is sometimes less than planned for when the etch recipe is established. One of the subsequent etch process segments, polysilicon main etch (PME) step, is not reliably selective. As a consequence there is a risk that oxide material under the polysilicon material will be etched by the PME step. In extreme occasions of such oxide etching microtrenching occurs near the transistor gate. The microtrenching may be reduced or eliminated by manually reducing the processing interval for the PME step. However, such a manual adjustment process is not useful for an automated system of the sort desired for achieving high throughput in semiconductor device manufacturing.
It would be desirable to be able to maintain the polysilicon end point (PEP) processing interval as constant and as short as possible. In particular it would be desirable to provide a method for controlling a process for manufacturing semiconductor devices that assures a short and substantially constant processing interval for a polysilicon end point (PEP) etching segment.
Maintaining polysilicon end point (PEP) processing interval constant at a short interval provides several advantages. In particular, by controlling the PEP etch processing interval one can significantly reduce the occurrence of punchthrough. Further, PEP etch is usually carried out in a condition in which contaminants tend to build up within the chamber in which the etch is carried out. Periodic chamber cleaning is therefore required. Such cleaning operations interfere with production and significantly reduce the yield and throughput of a manufacturing process. Reducing PEP etch processing intervals to a minimum serves to reduce times of contaminant build up and therefore increases intervals between required cleaning of the chamber and tools, improving the process throughput.
Another consideration that makes PEP processing interval reduction advantageous is the fact that this step affects differently n-material and p-material used in fabricating n-type and p-type transistors. The PEP step, unlike the preceeding steps, does not contain fluorine (F), which does not differentiate between the n-type and p-type material. The CDs are set-up by the preceeding steps, but the PEP step will have an influence on the CDs. Therefore, the PEP step should be kept short and fixed to minimize the difference between the n-type and p-type transistor CDs.
A method for dynamically controlling a semiconductor manufacturing process for producing a semiconductor component includes performing a plurality of process segments. Each respective process segment is performed for a respective processing interval. The method includes the steps of: (a) determining a relationship among respective process intervals for at least two particular process segments of the plurality of process segments; (b) determining a first respective process interval required for a first particular process segment to effect a desired result in the semiconductor component; and (c) using the relationship to establish the respective process interval required for at least one selected particular process segment in order to fix the respective process interval for a controlled process segment other than the at least one selected particular process segment.
It is, therefore, an object of the present invention to provide a method for controlling a process for manufacturing semiconductor devices that assures a short and substantially constant processing interval for a polysilicon end point (PEP) etching segment.
Further objects and features of the present invention will be apparent from the following specification and claims when considered in connection with the accompanying drawings, in which like elements are labeled using like reference numerals in the various figures, illustrating the preferred embodiments of the invention.